例えばこんなんでいいかな
https://cs.stanford.edu/people/eroberts/courses/soco/projects/2000-01/risc/whatis/
Certain design features have been characteristic of most RISC processors:
one cycle execution time: RISC processors have a CPI (clock per instruction) of one cycle. This
is due to the optimization of each instruction on the CPU and a technique called ;
pipelining: a techique that allows for simultaneous execution of parts, or stages, of instructions
to more efficiently process instructions;
large number of registers: the RISC design philosophy generally incorporates a larger number of
registers to prevent in large amounts
前二つは昔の実装技術レベルの話で、最初のはサイクルあたり複数命令とかすらあるし、二つ目はCISC
でも今時当たり前だから、どっちも本質じゃないのはいいかな
